The present invention disclosed herein relates to semiconductor devices and particularly, to nonvolatile memory devices and methods of operation thereof.
Semiconductor memory devices may be generally classified into volatile and nonvolatile types.
Volatile semiconductor memory devices may provide high read and write rates, but generally may lose their data when there is no power supply. Nonvolatile semiconductor memory devices are able to retain their data even without power supply. Thus, the nonvolatile semiconductor devices are widely used in applications requiring data retentivity regardless of power supply. There are many kinds of nonvolatile semiconductor memories including mask read-only memories (MROMs), programmable ROMs (PROMs), erasable and programmable ROMs (EPROMs), electrically erasable and/or programmable ROMs (EEPROMs), among others.
Generally, it may be inconvenient for users to update information from MROMs, PROMs, and EPROMs because those memories are not easily erased and written with data systemically in themselves. In contrast, EEPROMs may be electrically erased and written with data and are increasing used for subsidiary storage units or system programming tools that necessitate steady data updates. Flash EEPROMs can be fabricated in higher integrating density than traditional EEPROMs, which may be useful in applications with large capacity subsidiary memory units. One type of the flash EEPROM, NAN D-type flash EEPROMs (hereinafter, referred to as ‘NAND flash memories’), may be more advantageous to integration density than other types of the flash EEPROMs.
In flash memories, an available programmed state of a memory cell is determined by the number of bits stored in the memory cell. A memory cell storing 1-bit data (or a single data bit) is referred to as ‘single-bit cell’ or ‘single-level cell’ (SLC). A memory cell storing multi-bit data (or two or more data bits) is referred to as ‘multi-bit cell’, ‘multi-state cell’, or ‘multi-level cell’ (MLC). With increasing demands for high-density memory devices in recent years, significant interest has been generated regarding multi-level flash memories in which multi-bit data is stored in each memory cell.
Programming flash memory cells may include first erasing the memory cells to have a predetermined threshold voltage (e.g., −3V). Then, a substantial programming operation is conducted for selected memory cells by applying a high voltage (e.g., 20V) to a word line coupled to the selected memory cells.
In an SLC scheme, a programmed memory cell is conditioned in one of two threshold voltage distributions, which correspond to data states ‘1’ and ‘0’, respectively. In contrast, in an MLC scheme, a programmed memory cell is conditioned in one of N threshold voltage distributions, which correspond to N programmed states, respectively. Confining threshold voltage distributions within their respective threshold voltage windows in correspondence each with N programmed states may include densely controlled threshold voltage distributions. For this control, an incremental step-pulse programming (ISPP) scheme is being employed in programming flash memories. According to the ISPP scheme, threshold voltage voltages shift by an increment of a program voltage according to repetition of programming loops. In this regard, by establishing smaller increments of the program voltage, it may be possible to adjust threshold voltage distributions within more densely controlled voltage distributions.
Even with such an ISPP scheme, threshold voltage distributions of programmed states are formed wider than the desired widths of threshold voltage windows due to various reasons. For example, capacitive couplings between adjacent memory cells may cause threshold voltage distributions of programmed states to be narrower in the programming operation. This effect is called ‘electric field coupling’ or ‘F-poly coupling’. Narrower intervals between threshold voltage distributions of programmed states due to the electric field couplings may make it difficult to reliably read cell data. This problem becomes more serious as the number of data bits stored in a unit cell increases. Variation rates of threshold voltages of adjacent memory cells by the couplings are proportional to those of programmed memory cells. Thus, while programming erased memory cells, which have threshold voltage distributions extending from −3V, into other states, threshold voltages of adjacent memory cells may vary with increasing rates.